If you have never worked in the semiconductor industry, much of what goes on seems like intentionally obfuscated jargon and black magic. And for many years it was – or at least it seemed to be – as empirical knowledge outstripped theoretical understanding, and yields were more a factor of skilled process engineers at the knobs than of robust and thoroughly understood processes running in statistical control.
When I got involved in the semiconductor industry, wafer size was 100mm (4 inches) with a ‘flat’ along one or both edges, and a rather ‘generous’ edge exclusion area and ‘kerf’ between device chips on each wafer. Given the size of devices at the time, there wasn’t much room to pack too many devices per wafer. Soon device makers moved to 150mm (6″) wafers, at first with a flat but later with a small notch for alignment, and soon the race for ‘packing density’ was on!
Packing density was a two-prong operation. First off device makers wanted to shrink their devices to occupy as little space as possible, thereby consuming less real estate in whatever product used them. At the same time, they wanted to squeeze as many devices as possible on a single wafer. The reason for that should be obvious – if a given unit operation takes a fixed amount of time per wafer, getting more chips per wafer will decrease the per-chip cost and increase throughput.
But by putting more chips on a wafer, it increases testing requirements and time, and makes the fight to maximize yield even more challenging. This is because some processes spin the wafer and have radial sources of error, while others have large-field effects that have different error profiles and so on. So the larger the wafer and the more discrete elements per wafer, the harder to deal with the different sources of variation.
When 200mm (8″) wafers first came into large-scale testing, suddenly new technical challenges appeared: the spin radius of these larger wafers resulted in an extremely difficult time processing, needing new equipment designs for many processes. Also, moving these wafers around with high-speed robots built up charges that could short-circuit an entire wafer full of chips – valued at $100,000 a decade or so ago.
300mm brought more of the same in terms of challenges – new equipment, dealing with greater physics issues, and more value at risk per wafer. There were now electrostatic precipitators all over the FAB, measures for how much bow or warp was induced through the process, and so on.
So again – why do it? Well, if we assume the ‘normal’ packing density rules, standard kerf and dicing rules, for a 10mm x 10mm integrated circuit we could fit 270 chips on a 200mm wafer and 652 (!) on a 300mm wafer! Even if the die yield for the 200mm process was 80% (very good), the 300mm process would have to drop to an abysmal 30% yield before it lost the die advantage. Of course since equipment becomes more expensive at larger sizes there is a need for improved efficiency.
Moving to a new wafer size has become increasingly difficult for a number of reasons, which can all pretty much be summed up as ‘money’. The stage size and robotics to move a 450mm wafer is larger than the whole photolithographic system for 200mm! And due to ever-shrinking error budgets the flatness and vibration the cost to build equipment and facilities has skyrocketed. As a single example, the cost for a lithography stepper for 2 micron features (so-called ‘G-line’) on 100mm wafers was about $300,000 … and in 2007 the price for a 193nm litho system to produce 22nm features on 200mm wafers was $15 million – and close to $20 million for an equivalent 300mm configuration!
So it was really cool to hear that in spite of all of the risks and challenges, 450mm wafer processing efforts have started to take off! Here is a quote from a:
we have had a slew of announcements on 450 mm, the biggest of which was the joint ASML/Intel notice that Intel will be taking a share of ASML as a way of funding 450 mm and EUV R&D. Simultaneously imec released that the Flemish government would invest in their upcoming 450-mm facility, and imec and KLA-Tencor declared that a 450-mm capable SP3 450 unpatterned wafer defect inspection tool had been installed at imec.
ASML announced it as a “co-investment program” in which Intel would invest EUR829 million (about $1B) over the next five years, EUR553M of which would be in 450 mm R&D. Intel focused more on the R&D and described the financial details later.
They cited the classic economics of doubling the wafer size, and the potential die cost reduction:
All of which is logical, but ASML has been notably reticent about making any comments on 450-mm R&D in the past, to the point where some industry watchers (including me) have wondered if we would ever get there; if the biggest litho vendor isn’t on board, there won’t be any 450-mm fabs even if all the other equipment companies are ready.
Which brings me to the elephant in the title. Last year at Semicon there was a 450 mm panel, and everyone was pontificating wisely, until Bob Johnson of Gartner commented on “the elephant in the room – ASML has no 450-mm program, so why are we bothering to even talk about it?” (my paraphrasing). Which kind of shut the whole thing down.
However, that particular pachyderm has clearly moved on, and we have an ASML roadmap with both 450 mm and EUV in it:
If you look at some of the details, you’ll see that Intel is pouring more than $3 BILLION into ASML, the leading maker of lithography equipment. This means two things – that this new size is going to happen … and it is going to cost a ton of money.
Are you still awake at this point? If so you might be asking … WHY do I care? It is a fair question – but look at the recently released Nexus 7. Nearly two years ago Samsung introduced the Galaxy Tab, which was adequate but had a rather pokey single core processor and cost $400 for the base model. Now we have the Nexus 7 with a quad-core high performance SOC (system on a chip) with a very capable GPU as well … all for $199!
These changes – more power for less money and requiring lower battery power – are all about the advances in FAB technology. Shrinking the line and die size allows for lower current requirements, which means less heat dissipation – and that shrink allows for the die to take up more space, thereby allowing designers to pack more per wafer. This lowers the per-die costs, and increasing the wafer size means an even greater per-die savings. Companies such as Intel have seen at least 40% per-die cost reductions in the move from 150mm to 200mm to 300mm, and are assuming that the 450mm change will provide similar benefits.
In fact, Intel has been gambling on 450mm wafers for a while, as noted in this late 2010 report stating that the construction of their Oregon-based D1X FAB was based around 450mm equipment even before it would be available. But now with the ASML venture – ASML has a virtual monopoly in lithography exposure tools – it finally seems like 450mm will become ‘real’.
And as exciting as the pure technology is to me, it is the promise of amazing new capabilities at even lower prices that really gets me buzzing.